This paper was presented as a portion of a Ph. D. Qualifying Exam in August 1999.

A Framework for Real-Time High-Throughput Signal and Image Processing Systems on Workstations

Ph.D. Qualifying Proposal


Computer Engineering Area

Department of Electrical and Computer Engineering

The University of Texas at Austin


Submitted by Gregory E. Allen, B.S.E.E., M.S.E.

gallen AT arlut DOT utexas DOT edu


Committee Members:

Prof. James C. Browne (Dept. of CS)

Prof. Craig M. Chase (Dept. of ECE), chairman

Prof. Brian L. Evans (Dept. of ECE), advisor

Prof. Lizy K. John (Dept. of ECE)

Dr. Charles M. Loeffler (ARL:UT)



Real-time data-intensive systems such as sonar beamformers and synthetic aperture radar processors have traditionally required implementation in expensive custom hardware. Current systems use off-the-shelf programmable processors in customized configurations to reduce development cost. To reduce development cost and time further, we consider the use of workstations as the target architecture and design environment. We present a general approach for realizing real-time data-intensive systems in software on a multiprocessor workstation.

First, we present several dataflow models which are commonly used to describe systems of this nature. Second, we present a framework for developing scalable software implementations of signal and image processing systems on workstations. The framework models the concurrency and parallelism in these systems using Process Networks. The Process Network model guarantees determinate execution of concurrent programs regardless of the scheduling algorithm used. We employ a scheduling algorithm that always finds a bounded execution if one exists. Third, we implement the framework in C++ using lightweight real-time POSIX threads.

We use two case studies to evaluate the performance of our framework: a high-resolution 3-D sonar beamformer, and a synthetic aperture radar processor. On a Sun Ultra Enterprise workstation, the 4-GFLOP beamformer exhibits near-linear speedup using 1 to 12 processors and executes in real-time with 12 336-MHz UltraSPARC-II processors.

The full paper and slides from the presentation in PDF.

For more information contact: Greg Allen <gallen AT arlut DOT utexas DOT edu>